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FEATURES 64 Position Replaces Four Potentiometers 10 k , 100 k Power Shutdown--Less than 5 A 3-Wire SPI-Compatible Serial Data Input 10 MHz Update Data Loading Rate +2.7 V to +5.5 V Single Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Programmable Filters, Delays, Time Constants Volume Control, Panning Line Impedance Matching Power Supply Adjustment
SDI VDD DGND
4-Channel, 64-Position Digital Potentiometer AD5203
FUNCTIONAL BLOCK DIAGRAM
DAC 1
AD5203
6-BIT LATCH 6 CK RS 1 SHDN
A1 W1 B1 AGND1
DAC 2 SELECT 3 4 A1, A0 2 8-BIT SERIAL LATCH D CK Q RS
DAC 2 6-BIT 6 LATCH CK RS SHDN A2 W2 B2 AGND2
DAC 3 6 6-BIT LATCH 6 CK RS SHDN A3 W3 B3 AGND3
GENERAL DESCRIPTION
CLK CS 6-BIT LATCH CK RS 6
The AD5203 provides a quad channel, 64-position digitallycontrolled variable resistor (VR) device. These parts perform the same electronic adjustment function as a potentiometer or variable resistor. The AD5203 contains four independent variable resistors in a 24-lead SOIC and the compact TSSOP-24 packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k, or 100 k has a 1% channel-tochannel matching tolerance with a nominal temperature coefficient of 700 ppm/C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last 6-bits are data. A serial data output pin at the opposite end of the serial register allows simple daisychaining in multiple VR applications without additional external decoding logic.
DAC 4
SHDN
A4 W4 B4 AGND4
SDO
RS
SHDN
The reset RS pin forces the wiper to the midscale position by loading 20H into the VR latch. The SHDN pin forces the resistor to an end-to-end open circuit condition on terminal A and shorts the wiper to terminal B, achieving a microwatt power shutdown state. When shutdown is returned to logic-high the previous latch settings put the wiper in the same resistance setting prior to shutdown. The AD5203 is available in a narrow body P-DIP-24, the 24-lead surface mount package, and the compact 1.1 mm thin TSSOP-24 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For pin compatible higher resolution applications, see the 256position AD8403 product.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD5203-SPECIFICATIONS = +3 V (V
DD
ELECTRICAL CHARACTERISTICS otherwise noted)
Parameter Symbol Conditions
10% or +5 V
10%, VA = +V DD, VB = 0 V, -40 C < TA < +85 C unless
Min -0.25 -0.5 -30 Typ1 0.1 0.1 700 45 0.2 6 -0.25 -0.75 -0.75 0 0 Max +0.25 +0.5 +30 100 1 Units LSB LSB % ppm/C % Bits LSB LSB ppm/C LSB LSB V pF pF A V V V V V V A pF V A mA W %/% %/% kHz kHz % s s nV/Hz nV/Hz dB ns ns ns ns ns ns ns ns
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL RWB , VA = No Connect R-INL RWB , VA = No Connect Resistor Nonlinearity Error2 RAB Nominal Resistor Tolerance 3 VAB = V DD, Wiper = No Connect Resistance Temperature Coefficient RAB/T IW = 1 V/RAB Wiper Resistance RW Nominal Resistance Match R/RO CH 1 to CH 2, V AB = VDD , TA = +25C DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N DNL Differential Nonlinearity Error4 INL Integral Nonlinearity Error4 Code = 20H Voltage Divider Temperature Coefficient VW/T Code = 3FH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Supply Current7 Shutdown Wiper Resistance DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current (CMOS) Supply Current (TTL)8 Power Dissipation (CMOS)9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 10 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk11 VA, VB, VW CA, C B CW IA_SD RW_SD VIH VIL VIH VIL VOH VOL IIL CIL VDD Range IDD IDD PDISS PSS PSS BW_10K BW_100K THDW tS _10K tS _100K e NWB CT
0.1 0.1 20 -0.2 +0.1
+0.25 +0.75 0 +0.75 VDD
f = 1 MHz, Measured to GND, Code = 20H f = 1 MHz, Measured to GND, Code = 20H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V VDD = +5 V VDD = +5 V VDD = +3 V VDD = +3 V RL = 2.2 k to VDD IOL = 1.6 mA, VDD = +5 V VIN = 0 V or +5 V, VDD = +5 V 2.4
75 120 0.01 45
5 100
0.8 2.1 0.6 VDD -0.1 0.4 1 5 2.7 5.5 5 4 27.5 0.001 0.03
VIH = V DD or VIL = 0 V VIH = 2.4 V or VIL = 0.8 V, V DD = +5.5 V VIH = V DD or VIL = 0 V, V DD = +5.5 V VDD = +5 V 10% VDD = +3 V 10% RAB = 10 k RAB = 100 k VA =1 V rms + 2 V dc, V B = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, 1 LSB Error Band VA = VDD, VB = 0 V, 1 LSB Error Band RWB = 5 k, f = 1 kHz, RS = 0 RWB = 50 k, f = 1 kHz, RS = 0 VA = VDD, VB = 0 V 10 5 5 1 10 10 50 0
0.01 0.9 0.0002 0.006 600 71 0.003 2 18 9 29 -65
INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 12 Input Clock Pulsewidth tCH , tCL Clock Level High or Low Data Setup Time tDS Data Hold Time tDH tPD RL = 2.2 k, CL < 20 pF CLK to SDO Propagation Delay13 CS Setup Time tCSS CS High Pulsewidth tCSW Reset Pulsewidth tRS CLK Fall to CS Rise Hold Time tCSH
25
CS Rise to Clock Rise Setup
tCS1
10
ns
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NOTES 1 Typicals represent average readings at +25C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3 VAB = V DD, Wiper (VW ) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and V B = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode. 8 Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage inputs result in minimum power dissipation. 9 PDISS is calculated from (I DD x V DD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. 12 See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +3 V or +5 V. Input logic should have a 1 V/ s minimum slew rate. 13 Propagation delay depends on value of V DD, R L and C L. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C, unless otherwise noted)
SDI
1 A1 A0 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 CS 0 VOUT VDD 0V DAC REGISTER LOAD
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD IAB, IAW, I BW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Package Power Dissipation . . . . . . . . . . . . . . (T J max-TA)/JA Thermal Resistance JA P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1a. Timing Diagram
SDI (DATA IN) 1 Ax OR Dx 0 1 A'x OR D'x 0 A'x OR D'x Ax OR Dx
t DS
t DH
SDO (DATA OUT)
t PD
MIN
t PD
MAX
1 CLK 0
t CH
t CS1 t CL t CSH t CSW tS
1 LSB ERROR BAND 1 LSB
t CSS
1 CS 0 VOUT VDD 0V
Table I. Serial-Data Word Format
ADDR B7 B6 A1 MSB 27 A0 LSB 26
DATA B5 B4 D5 MSB 25 D4
B3 D3
B2 D2
B1 D1
B0 D0 LSB 20
Figure 1b. Detail Timing Diagram
t RS tS
1 LSB 1 LSB ERROR BAND
1 RS 0 VDD VOUT 0V
Figure 1c. Reset Timing Diagram
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD5203
PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS
AGND2 B2 A2 W2 AGND4 B4 A4 W4 DGND
1 2 3 4 5 6 7 8 9
24 23 22 21
B1 A1 W1 AGND1 B3
Pin No. 1 2 3 4 5 6 7 8 9 10
Name AGND2 B2 A2 W2 AGND4 B4 A4 W4 DGND SHDN
Description Analog Ground #2* B Terminal RDAC #2 A Terminal RDAC #2 Wiper RDAC #2, addr = 012 Analog Ground #4* B Terminal RDAC #4 A Terminal RDAC #4 Wiper RDAC #4, addr = 112 Digital Ground* Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistors #1 through #4. Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register. Serial Data Input Serial Data Output. Open drain transistor requires pull-up resistor. Serial Clock Input, positive edge triggered. Active low reset to midscale; sets RDAC registers to 20H . Positive power supply, specified for operation at both +3 V and +5 V. Analog Ground #3* Wiper RDAC #3, addr =102 A Terminal RDAC #3 B Terminal RDAC #3 Analog Ground #1* Wiper RDAC #1, addr = 002 A Terminal RDAC #1 B Terminal RDAC #1
AD5203
20
(Not to Scale) 19 A3
18 17 16 15 14 13
W3 AGND3 VDD RS CLK SDO
SHDN 10 CS 11 SDI 12
11
CS
12 13 14 15 16 17 18 19 20 21 22 23 24
SDI SDO CLK RS VDD AGND3 W3 A3 B3 AGND1 W1 A1 B1
*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
Model AD5203AN10 AD5203AR10 AD5203ARU10 AD5203AN100 AD5203AR100 AD5203ARU100
k 10 10 10 100 100 100
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Descriptions 24-Lead Narrow Body Plastic DIP 24-Lead Wide Body (SOIC) 24-Lead Thin Surface Mount Package (TSSOP) 24-Lead Narrow Body Plastic DIP 24-Lead Wide Body (SOIC) 24-Lead Thin Surface Mount Package (TSSOP)
Package Options N-24 SOL-24 RU-24 N-24 SOL-24 RU-24
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Typical Performance Characteristics- AD5203
10 9 8 VWB VOLTAGE - V RESISTANCE - k 7 6 5 4 3 2 1 0 0 8 16 24 32 40 48 CODE - Decimal 56 64 RWB RWA VDD = +3V, OR +5V RAB = 10k 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 RAB = 10k VDD = +5V TA = +25 C 2 3 4 5 IWA CURRENT - mA 6 7 02H 20H 10H RINL ERROR - LSB 08H 05H 3FH 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 16 24 32 40 48 56 8 DIGITAL INPUT CODE - Decimal 64 TA = -55 C TA = +25 C TA = +85 C VDD = +3.0V
Figure 2. Wiper to End Terminal Resistance vs. Code
Figure 3. Resistance Linearity vs. Conduction Current
Figure 4. Resistance Step Position Nonlinearity Error vs. Code
80 SS = 544 UNITS VDD = +4.5V TA = +25 C 60 FREQUENCY
12
AD5203-10K VERSION INL NONLINEARITY ERROR - LSB
0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 8 16 24 32 40 48 56 DIGITAL INPUT CODE - Decimal 64 -55 C +85 C +25 C VDD = +3.0V
10 NOMINAL RESISTANCE - k
RAB (END-TO-END)
8
40
6 RWB (WIPER-TO-END) CODE = 20H
4
20
2 0 0 25 50 75 -75 -50 -25 TEMPERATURE - C
0 30 31 32 33 34 35 36 37 38 39 WIPER RESISTANCE -
100 125
Figure 5. Wiper-Contact-Resistance Histogram
Figure 6. Nominal Resistance vs. Temperature
Figure 7. Potentiometer Divider Nonlinearity Error vs. Code
POTENTIOMETER MODE TEMPCO - ppm/ C
0.25 0.2 0.15 DNL ERROR - LSB 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 8 16 24 32 40 48 56 DIGITAL INPUT CODE - Decimal 64 VDD = +3.0V TA = +25 C, +85 C, -40 C
50 RHEOSTAT MODE TEMPCO - ppm/ C VDD = +3.0V TA = -40 C/+85 C VA = +2.0V VB = 0V
120 VDD = +3.0V TA = -40 C/+85 C VA = NO CONNECT RWB MEASURED
40
100
80
30
60
20
40
10
20
0
0 0 8 16 24 32 40 48 CODE - Decimal 56 64
0
8
16
24 32 40 48 CODE - Decimal
56
64
Figure 8. Potentiometer Divider Differential Nonlinearity Error vs. Code
Figure 9. VWB/T Potentiometer Mode Tempco
Figure 10. RWB/T Rheostat Mode Tempco
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AD5203-Typical Performance Characteristics
0 CODE = 3FH -10 20H 10H RW (20mV/DIV) GAIN - dB -20 08H 04H -30 02H 01H -40 TIME 500ns/DIV -50 10 TA = +25 C SEE TEST CIRCUIT FIGURE 32 100 1k 10k 100k FREQUENCY - Hz 1M 10M RWB RESISTANCE - % 0.5 0.75 VDD = +5V CODE = 3FH SS = 77 UNITS AVG +2 AVG AVG -2 -0.25
0.25
0
CS (5V/DIV)
-0.5
-0.75
0
200 300 400 500 100 HOURS OF OPERATION @ 150 C
600
Figure 11. One Position Step Change at Half-Scale (Code 1FH to 20H)
Figure 12. Gain vs. Frequency for R = 10 k
Figure 13. Long-Term Drift Accelerated by Burn-In
10 FILTER = 22kHz VDD = +5V TA = +25 C RAB = 10k VOUT (20mV/DIV) SEE TEST CIRCUIT FIGURE 31 0.01 SEE TEST CIRCUIT FIGURE 30 TIME 5 s/DIV 0.001 10 100 1k 10k FREQUENCY - Hz 100k TIME 100ns/DIV
1 OUTPUT THD + NOISE - %
0.1
CS
Figure 14. Large Signal Settling Time
Figure 15. Total Harmonic Distortion Plus Noise vs. Frequency
Figure 16. Digital Feedthrough vs. Time
CODE = 3FH -10 20H 10H GAIN - dB -20 08H 04H -30 02H VDD = +5V TA = +25 C 5dB/DIV 100 01H
NORMALIZED GAIN FLATNESS - 0.1dB/DIV
0
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 10 VDD = +5V CODE = 3FH TA = +25 C SEE TEST CIRCUIT FIGURE 32 100 1k 10k 100k FREQUENCY - Hz 1M RAB = 100k RAB = 10k IDD SUPPLY CURRENT - mA
10
VDD = +5.0V 1
0.1
VDD = +3.0V
-40
-50 10
0.01 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 INPUT LOGIC VOLTAGE - Volts 5
1k 10k 100k FREQUENCY - Hz
1M
Figure 17. 100 k Gain vs. Frequency vs. Code
Figure 18. Normalized Gain Flatness vs. Frequency
Figure 19. Supply Current vs. Logic Input Voltage
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80 0 -5 IDD - SUPPLY CURRENT - A 1000 60 PSRR - dB GAIN - dB -10 -15 -20 -25 -30 -35 -40 -45 1M -50 10 VDD = +5V VIN = 100mV rms CODE = 20H TA = +25 C 100 1k 10k FREQUENCY - Hz 100k 1M f-3dB = 65kHz, R = 100k f-3dB = 625kHz, R = 10k 1200 A - VDD = +5.5V CODE = 15H B - VDD = +3.3V CODE = 15H C - VDD = +5.5V CODE = 3FH D - VDD = +3.3V CODE = 3FH B TA = +25 C
800
40
600
VDD = +5V DC 1V p-p AC 20 TA = +25 C CODE = 80H CL = 10pF VA = 4V, VB = 0V 0 1k 10k 100k FREQUENCY - Hz
400 A 200
C D 10k 100k 1M FREQUENCY - Hz 10M
0 1k
Figure 20. Power Supply Rejection vs. Frequency
Figure 21. -3 dB Frequency at Half-Scale
Figure 22. Supply Current vs. Clock Frequency
100 TA = +25 C
100 VDD = +5V IA SHUTDOWN CURRENT - nA IDD - SUPPLY CURRENT - A
1 LOGIC INPUT VOLTAGE = 0, VDD
80 VDD = +2.7V 60 RON -
0.1
10
40
VDD = +5.5V
0.01 VDD = +5.5V
20
0
0
1
2
3 4 VDD - Volts
5
6
1 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE - C
VDD = +3.3V 0.001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C
Figure 23. Incremental Wiper ON Resistance vs. VDD
Figure 24. Shutdown Current vs. Temperature
Figure 25. Supply Current vs. Temperature
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AD5203-Parametric Test Circuits
A DUT A W B V+ = VDD 1LSB = V+/64 OFFSET GND DUT B W +5V VIN
~
V+
OP279
VMS 2.5V DC
VOUT
Figure 26. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
Figure 30. Inverting Programmable Gain Test Circuit
+5V NO CONNECT DUT A W B VMS IW OFFSET GND 2.5V VIN
~
A
W
OP279
VOUT
DUT
B
Figure 27. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 31. Noninverting Programmable Gain Test Circuit
IMS V+ DUT A W B VMS VW IW = 1V/RNOMINAL VDD VIN OFFSET GND A +15V W DUT B 2.5V VW2 - [VW1 + I W (RAW II R BW)] RW = -------------------------- IW WHERE VW1 = VMS WHEN I W = 0 AND VW2 = VMS WHEN IW = 1/R
~
V+
OP42
-15V
VOUT
Figure 28. Wiper Resistance Test Circuit
Figure 32. Gain vs. Frequency Test Circuit
VA V+ = VDD 10% V+
MS ( ----- ) V DD
DUT V W B ISW PSRR (dB) = 20 LOG VMS VMS% PSS (%/%) = ------- VDD%
RSW = 0.1V ISW CODE = OOH 0.1V
~
VDD
A B
W
0 TO VDD
Figure 29. Power Supply Sensitivity Test Circuit (PSS, PSRR)
Figure 33. Incremental ON Resistance Test Circuit
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OPERATION
The AD5203 provides a quad channel, 64-position digitallycontrolled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in an 8-bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is two address bits, MSB first, followed by six data bits, MSB first. Table I provides the serial register data word format. The AD5203 has the following address assignments for the ADDR decode, which determines the location of VR latch receiving the serial register data in Bits B5 through B0: VR# = A1 x 2 + A0 + 1 VR outputs can be changed one at a time in random sequence. The serial clock running at 10 MHz makes it possible to load all four VRs in under 3.2 s (8 x 4 x 100 ns) for the AD5203. The exact timing requirements are shown in Figure 1. The AD5203 resets to a midscale by asserting the RS pin, simplifying initial conditions at power-up. Both parts have a power shutdown SHDN pin that places the RDAC in a zero power consumption state where terminals Ax are open-circuited and the wiper Wx is connected to Bx, resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values.
RS Ax
tap point located at 201 [= RBA(nominal resistance)/64 + RW = 156 + 45 )] for data 01 H. The third connection is the next tap point representing 312 + 45 = 357 for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9889 . The wiper does not directly connect to the B Terminal. See Figure 34 for a simplified diagram of the equivalent RDAC circuit. The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is: R WB(Dx) = (Dx)/64 x R BA + RW (1) where Dx is the data contained in the 6-bit RDACx latch and RBA is the nominal end-to-end resistance. For example, when VB = 0 V and A-terminal is open circuit the following output resistance values will be set for the following RDAC latch codes (applies to the 10K potentiometer): D (DEC) RWB ( ) 63 32 1 0 9889 5045 201 45 Output State Full-Scale Midscale (RS = 0 Condition) 1 LSB Zero-Scale (Wiper Contact Resistance)
SHDN
Note that in the zero-scale condition a finite wiper resistance of 45 is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. When these terminals are used the B-terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: R WA(Dx) = (64-Dx)/64 x R BA + R W (2) where Dx is the data contained in the 6-bit RDACx latch and RBA is the nominal end-to-end resistance. For example, when VA = 0 V and B-terminal is tied to the wiper W, the following output resistance values will be set for the following RDAC latch codes: D (DEC) RWA ( ) 201 5045 9889 10045 Output State Full-Scale Midscale (RS = 0 Condition) 1 LSB Zero-Scale
RS D5 D4 D3 D2 D1 D0 RDAC LATCH & DECODER
RS
Wx
RS RS = RAB /64
Bx
Figure 34. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistance of the RDAC between Terminals A and B are available with values of 10 k, and 100 k. The final digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 100 k = 100. The nominal resistance (RAB) of the VR has 64 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-bit data word in the RDAC latch is decoded to select one of the 64 possible settings. The wiper's first connection starts at the B terminal for data 00H . This B-terminal connection has a wiper contact resistance of 45 . The second connection (10 k part) is the first
63 32 1 0
The typical distribution of RBA from channel to channel matches within 1%. However, device-to-device matching is process-lotdependent, having a 30% variation. The change in RBA with temperature has a 700 ppm/C temperature coefficient.
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PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to +5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 64 position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(Dx) = Dx/64 x VAB + VB Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore the drift improves to 20 ppm/C.
DIGITAL INTERFACING
The AD5203 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. The Figure 35 block diagram shows more detail of the internal digital circuitry. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table III.
CS CLK EN A1 DO A0 D5 ADDR DEC D5
The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package's SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply of the AD5203 SDO output device, e.g., the AD5203 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining several RDACs from a single processor serial data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding location. This would require 16 bits of address and data complying to the word format provided in Table I if two AD5203 fourchannel RDACs are daisy chained. During shutdown, SHDN the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. See Figure 37 for equivalent SDO output circuit schematic.
Table II. Input Logic Control Truth Table
CLK CS L P L L
RS H H
SHDN Register Activity H H No SR effect, enables SDO pin. Shift one bit in from the SDI pin. The eighth previously entered bit is shifted out of the SDO pin. Load SR data into RDAC latch based on A1, A0 decode (Table III). No Operation. Sets all RDAC latches to midscale, wiper centered and SDO latch cleared. Latches all RDAC latches to 20H . Open circuits all Resistor A-terminals, connects W to B, turns off SDO output transistor.
X X X
P H X
H H L
H H H
AD5203
R DAC LAT #1 R
VDD A1 W1 B1
SDO
D0
X X
H H
P H
H L
SER REG D5 SDI DI D0 6 SHDN DGND RS AGND D0 A4 R DAC LAT #4 R W4 B4
NOTE: P = positive edge, X = don't care, SR = shift register.
Table III. Address Decode Table
A1 0 0 1 1
A0 0 1 0 1
Latch Decoded RDAC#1 RDAC#2 RDAC#3 RDAC#4
Figure 35. Block Diagram
-10-
REV. 0
AD5203
The data setup and data hold times in the specification table determine the data valid time requirements. The last eight bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder which enables one of four positive edge triggered RDAC latches, see Figure 36 detail.
AD5203
CS ADDR DECODE RDAC 1 RDAC 2 RDAC 4 CLK SDI SERIAL REGISTER
All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 38. Applies to digital input pins CS, SDI, SDO, RS, SHDN, CLK.
1k LOGIC
Figure 38. Equivalent ESD Protection Circuit
DYNAMIC CHARACTERISTICS
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the serial data word completing one RDAC update. Four separate 8-bit data words must be clocked in to change all four VR settings.
SHDN CS SDI SERIAL REGISTER D Q SDO
CK RS CLK RS
The total harmonic distortion plus noise (THD+N) measures 0.003% using an offset ground with a rail-to-rail OP279 inverting op amp test circuit, see Figure 30. Figure 15 plots THD versus frequency for both inverting and noninverting amplifier topologies. Thermal noise is primarily Johnson noise, typically 9 nV/Hz for the 10 k version measured at 1 kHz. For the 100 k device, thermal noise measures 29 nV/Hz. Channel-tochannel crosstalk measures less than -65 dB at f = 100 kHz. To achieve this isolation, the extra ground pins (AGND) located between the potentiometer terminals (A, B, W) must be connected to circuit ground. The AGND and DGND pins should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power supply rejection is typically -50 dB at 10 kHz (care is needed to minimize power supply ripple injection in high accuracy applications).
Figure 37. Detail, SDO Output Schematic of the AD5203
REV. 0
-11-
AD5203
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body Plastic DIP (N-24)
1.275 (32.30) 1.125 (28.60)
24 1 13 12
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
SEATING PLANE
0.015 (0.381) 0.008 (0.204)
24-Lead SOIC (SOL-24)
0.6141 (15.60) 0.5985 (15.20)
24 13
1
12
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
24-Lead Thin Surface Mount TSSOP (RU-24)
24
13
1
12
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
-12-
REV. 0
PRINTED IN U.S.A.
0.311 (7.90) 0.303 (7.70)
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
C3364-8-7/98

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